With the accelerating growth of Internet and intranet communication, high-bandwidth applications (such as streaming video), and large information databases, there has been an increase in the need not only for high-bandwidth I/O processing, but also for networked storage systems. Commonly elements within I/O systems include host bus adapters (HBAs) and redundant arrays of independent disks (RAID) controllers, both of which are commonly used with conventional bus protocols, such as peripheral component interface (PCI) or system packet interface level 4 (SPI-4) protocol.
FIG. 1 illustrates a conventional input/output (I/O) system 100 that includes a shared bus I/O controller 105. Shared bus I/O controller 105 further includes a PCI bridge 110 with an integrated exclusive OR (XOR) 112, a microprocessor 114, a memory 116, a first dual-port host bus adapter (HBA) 118 having a Port A and a Port B, a second dual-port HBA 120 likewise having a Port A and a Port B, and a dynamic random access memory (DRAM) 122. Furthermore, shared bus I/O controller 105 utilizes a pair of PCI-X buses. (The PCI-X specification is representative of a PCI bus with increased bandwidth capability, as is well known.) More specifically, PCI bridge 110 is electrically connected to Port A and Port B of dual-port HBA 118 via a PCI-X bus 124 and electrically connected to Port A and Port B of dual-port HBA 120 via a PCI-X bus 126, as shown in FIG. 1. Port A and Port B of dual-port HBA 118 and Port A and Port B of dual-port HBA 120 each have separate bi-directional paths connecting to PCI-X buses 124 and 126, respectively, also shown in FIG. 1. PCI-X buses 124 and 126 are shared buses, meaning both data and control information are handled via these buses.
Conventional I/O system 100 further includes a host 128, a host 130, a storage device 132, and a storage device 134; all external to shared bus I/O controller 105. In the example of FIG. 1, PCI-X bus 124 is dedicated to host port connections as illustrated by host 128 electrically connected to Port A of dual-port HBA 118 and host 130 electrically connected to Port B of dual-port HBA 120. Hosts 128 and 130 are representative of standard host or server applications. By contrast, PCI-X bus 126 is dedicated to back-end storage connections as illustrated by storage device 132 electrically connected to Port A of dual-port HBA 120 and storage device 134 electrically connected to Port B of dual-port HBA 120. Storage devices 132 and 134 are representative of standard storage devices, such as disk drives or tape controllers. Hosts 128 and 130 and storage devices 132 and 134 are electrically connected to their respective ports via a bus with full duplex capability.
PCI bridge 110 is a standard bridge device that communicates between a computer's microprocessor (in this case, microprocessor 114) and one or more local PCI buses (in this case are PCI-X buses 124 and 126). PCI bridge 110 is hardware commonly known in the art that also allows control/data information to pass from PCI-X bus 124 to PCI-X bus 126 and vice versa. Microprocessor 114 is any standard microcontroller device. In this application, microprocessor 114 serves as a memory controller that maps system memory into a bus-addressable architecture, such as PCI or PCI-X addressing schemes. PCI-X buses 124 and 126 are the primary data bus between microprocessor 114 and the outside world via dual-port HBAs 118 and 120. Microprocessor 114 may be, for example, a Pentium processor or a Power PC processor. Memory 116 is representative of any standard RAM/ROM device serving as local memory associated with microprocessor 114, as is well known.
Integrated within PCI bridge 110 is XOR 112, which is representative of an XOR engine that is programmed by microprocessor 114. XOR 112 is dedicated hardware for performing a well-known RAID function. For example, in RAID-5 or RAID-6 architecture, XOR 112 must calculate parity. Furthermore, electrically connected to PCI bridge 110 is DRAM 122. DRAM 122 is representative of memory that is mapped into the PCI space, so that DRAM 122 appears to reside on PCI-X bus 124 or 126.
Dual-port HBAs 118 and 120 are conventional devices for providing an interface connection between a SCSI device (such as a hard drive) and a processor, as is well known. Dual-port HBAs 118 and 120 are, for example, dual-port 4 Gb HBAs, such as those manufactured by QLogic Corporation (Aliso Viejo, Calif.). Dual-port HBAs 118 and 120 connect, for example, 800 MB/s buses with full duplex capability from their respective PCI-X buses to their respective external devices. More specifically, Port A of dual-port HBA 118 has an 800 MB/s fully duplexed bus connecting to host 128, Port B of dual-port HBA 118 has an 800 MB/s fully duplexed bus connecting to host 130, Port A of dual-port HBA 120 has an 800 MB/s fully duplexed bus connecting to storage element 132, and Port B of dual-port HBA 120 has an 800 MB/s fully duplexed bus connecting to storage element 134. On the PCI-X bus side of Ports A and B, dual-port HBAs 118 and 120 provide, for example, up to 1 GB/s of burst bandwidth available for either read or write transfers. Typical sustained bandwidth is around 800 MB/s. Since the PCI-X bus is a bi-directional bus, the available sustained bandwidth must be shared between read and write data bursts.
The operation of conventional shared bus I/O controller 105 is well known. In general terms, shared bus I/O controller 105 utilizes PCI-X bus 124 for to host port connections and PCI-X bus 126 for back-end storage connections. Both data and control information are handled via PCI-X buses 124 and 126. Shared bus I/O controller 105 is limited to a peak burst data rate of 2 Gb/s and a sustained bandwidth of 1.6 Gb/s by the PCI-X specifications. Also, latency is incurred when the direction of the bus changes between read and write bursts, as well as arbitration between the multiple clients on the shared bus. For example, dual-port HBAs 118 and 120 alone require 1.6 Gb/s of PCI-X bandwidth. Furthermore, the presence of the control information on PCI-X buses 124 and 126 uses PCI-X bus bandwidth and increases latency. Latency is most common when shared bus I/O controller 105 sends data out to a peripheral device, such as hosts 128 and 130 and storage elements 132 and 134, and must wait for the peripheral device to send a specific signal or set of data back.
Even though shared bus I/O controller 105, having separate host port connections and back-end storage connections, has improved bandwidth as compared with an I/O controller having only one PCI-X bus to direct all traffic, the bandwidth of shared bus I/O controller 105 is still constrained. Since both data and control information consume bandwidth, the amount of peripheral device traffic that may be sustained is physically limited to the bandwidth of the pair of shared PCI-X buses. Furthermore, all transactions take place serially to multiple peripheral devices on the limited bandwidth PCI-X buses, which will increase system latency.
The elements of shared bus I/O controller 105 (i.e., PCI bridge 110, XOR 112, microprocessor 114, memory 116, dual-port HBA 118, dual-port HBA 120, DRAM 122, PCI-X bus 124, and PCI-X bus 126) are typically discrete components arranged upon a printed circuit board (PCB). As a result, a further limitation in overall performance of shared bus I/O controller 105 is due to the lack of electrical integration. Lack of electrical integration inherently limits signal speed and signal integrity because of the physical distance between components.
Another example of an I/O controller is disclosed in U.S. Pat. No. 6,230,219, entitled, “High Performance Multi-channel DMA controller for a PCI Host Bridge with a Built-in Cache.” The '219 patent describes a host bridge having a dataflow controller. The host bridge contains a read command path, which has a mechanism for requesting and receiving data from an upstream device. The host bridge also contains a write command path that has means for receiving data from a downstream device and for transmitting received data to an upstream device. A target controller is used to receive the read and write commands from the downstream device and to steer the read command toward the read command path and the write command toward the write command path. A bus controller is also used to request control of an upstream bus before transmitting the request for data of the read command and transmitting the data of the write command.
Although the '219 patent describes a suitable I/O controller for performing write and read operations, the bandwidth of the bus is still shared between both command and data information. The fact that the bus is used for both commands and data, i.e., is a shared bus, adversely affects bandwidth on, for example, a PCI bus. The control information on the bus uses bandwidth that could otherwise be used for data. Hence, the control information has the propensity for causing a bottleneck for data flow. The shared bus also contributes to the problem of increasing latency, which is the amount of time that one part of a shared bus I/O controller spends waiting for requested data or acknowledge signals. Latency is most common when a shared bus I/O controller sends data to a peripheral device, such as a host or a storage device, and waits for the peripheral device to return specific data. Accordingly, a need exists for a way of overcoming the bandwidth limitations of I/O controllers having a shared bus architecture, thereby improving the overall performance.
It is therefore an object of the invention to provide an I/O controller architecture that meets the architectural requirement to stream on all I/O ports with maximum performance.
It is another object of this invention to provide an I/O controller architecture that handles the rate of existing I/O technology for connections to hosts and disks without being the bottleneck.
It is yet another object of this invention to provide hardware integration of an I/O controller to achieve maximum performance.